The present invention relates generally to a method of testing the processing of a semiconductor wafer on a CMP apparatus, and more particularly to a method of testing the processing of a semiconductor wafer on a CMP apparatus which utilizes the Preston Relationship.
Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on or in a surface of a wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer. In addition, a semiconductor wafer may be polished to remove surface defects such as scratches, roughness, or embedded particles of dirt or dust. Removing these surface defects improves the quality and reliability of the semiconductor wafer.
One system utilized to perform the above described polishing process is known as a chemical mechanical planarization apparatus. Polishing with a chemical mechanical planarization apparatus typically includes positioning a semiconductor wafer to be polished in contact with a polishing pad, and then moving the polishing pad and the semiconductor wafer relative to each other so as to cause material to be removed from the surface of the semiconductor wafer. Polishing with a chemical mechanical planarization apparatus also typically includes the introduction of a chemical slurry onto the surface of the semiconductor to facilitate the removal of material therefrom.
One draw back to utilizing the above described system to polish semiconductor wafers is that the calibration of the chemical mechanical planarization apparatus needs to be checked periodically to ensure that the processing parameters of the apparatus are equal to, or within a predetermined tolerance range of, control parameters. For example, processing parameters of the apparatus which need to be checked periodically include (i) the pressure between the semiconductor wafer surface and the polishing pad and (ii) the relative linear velocity between the semiconductor wafer surface and the polishing pad. If the processing parameters of the apparatus are not equal to, or within a predetermined tolerance range of, predetermined control parameters then the apparatus must be shut down and serviced before additional semiconductors wafers can be polished.
The above described process of periodically checking the processing parameters of the apparatus, and then servicing the apparatus if required, is time consuming and expensive and thus decreases efficiency of semiconductor wafer fabrication process. Therefore, a continuing need exists for a method of testing the processing of a semiconductor wafer on a chemical mechanical planarization apparatus.
In accordance with a first embodiment of the present invention, there is provided a method of testing the processing of a wafer on a CMP apparatus. The method includes (a) processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions, (b) performing a control wafer surface removal rate measurement for the control wafer during (a), (c) generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon (i) the control conditions utilized in (a) and (ii) the removal rate measurement of (b), (d) processing a test wafer with the CMP apparatus with a test consumable combination under a set of test conditions, wherein (i) the test consumable combination is intended to be substantially the same as the control consumable combination and (ii) the set of test conditions is intended to be substantially the same as the set of control conditions, (e) performing a test wafer surface removal rate measurement for the test wafer during (d), (f) generating a test data set which describes the processing of the test wafer with the CMP apparatus, the test data set being based upon (i) the test conditions utilized in (d) and (ii) the removal rate measurement of (e), and (g) comparing the test data set to the control data set.
Pursuant to a second embodiment of the present invention, there is provided method of testing the processing of a wafer on a CMP apparatus. The method includes (a) processing a test wafer with the CMP apparatus with a test consumable combination under a set of test conditions, wherein (i) the test consumable combination is intended to be substantially the same as a control consumable combination and (ii) the test wafer is intended to be substantially the same as a control wafer, (b) performing a test wafer surface removal rate measurement for the test wafer during (a), (c) generating a test data set which describes the processing of the test wafer with the CMP apparatus, the test data set being based upon (i) the test conditions utilized in (a) and (ii) the removal rate measurement of (b), and (d) comparing the test data set to a control data set, wherein the control data set describes the processing of a control wafer with the CMP apparatus utilizing the control consumable combination, the control data set being based upon (i) a set of control conditions and (ii) a control wafer surface removal rate measurement for the control wafer.
Pursuant to a third embodiment of the present invention, there is provided an a method of testing the processing of a wafer on a CMP apparatus. The method includes (a) processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions, (b) performing a control wafer surface removal rate measurement for the control wafer during (a) with an in-situ removal rate monitor, (c) generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon (i) the control conditions utilized in (a) and (ii) the removal rate measurement of (b), (d) processing a test wafer with the CMP apparatus with a test consumable combination under a set of test conditions, wherein (i) the test consumable combination is intended to be substantially the same as the control consumable combination and (ii) the set of test conditions is intended to be substantially the same as the set of control conditions, (e) performing a test wafer surface removal rate measurement for the test wafer during (d) with the in-situ removal rate monitor, (f) generating a test data set which describes the processing of the test wafer with the CMP apparatus, the test data set being based upon (i) the test conditions utilized in (d) and (ii) the removal rate measurement of (e), (g) comparing the test data set to the control data set so as to determine whether the test data set is the same or within a predetermined tolerance range of the control data set; and (h) alerting an operator of the CMP apparatus if the test data set is not the same or not within a predetermined tolerance range of the control data set.
It is an object of the present invention to provide a new and useful method of testing the processing of a wafer on a CMP apparatus.
It is also an object of the present invention to provide an improved method of testing the processing of a wafer on a CMP apparatus.
It is yet further an object of the present invention to provide method of testing the processing of a wafer on a CMP apparatus which enhances the semiconductor wafer fabrication process.